1. Field of the Invention
The present invention relates to a CMOS semiconductor integrated circuit device including inverter circuits of a plurality of output stages.
2. Description of the Related Art
A conventional CMOS semiconductor integrated circuit device having inverter circuits of a plurality of output stages is so constructed that a high electric potential is applied to the source regions of a plurality of P-channel MOS transistors through a common metal wiring layer formed on a substrate. The conventional device has a problem in which the degree of freedom of circuit arrangement is restricted. Moreover, the following problem arises. The final output stage whose output current capacity is large, is connected to a high-potential pad through the metal wiring layer as a feed path common to those of the other output stages. Therefore, an instantaneous variation in power source voltage caused when the final output stage is turned on or off, varies a voltage applied to the other circuits connected by the metal wiring layer, resulting in generation of switching noise and malfunction.
As a technique of eliminating the above problems, Published Unexamined Japanese Patent Application No. 64-89557 discloses a circuit arrangement in which a voltage is applied to the source region of a P-channel MOS transistor through a substrate. This circuit arrangement has the advantage of miniaturizing a device since the circuit arrangement is not restricted by a metal wiring layer and the advantage of suppressing generation of switching noise since the substrate has a large capacitance. In the arrangement, however, when the voltage is applied to a stage whose power consumption is high, such as the final stage, an operation speed of the stage is decreased since the resistance of the substrate comes to affect the speed.